FIG. 1 shows a test arrangement based on the prior art. A circuit to be tested DUT (device under test) is connected to an external test unit via a control bus, a data bus and an address bus. The external test unit uses a test data generator to produce test data which are applied via data bus lines in a data bus to the memory which is to be tested DUT. The address bus is used to address the memory cells which are to be tested within the memory which is to be tested. In this case, the test data are written to the address memory cells via the data bus and are subsequently read again. The external test unit compares the written test data with the data which have been read and recognizes from the discrepancies or data errors whether the addressed memory cells within the memory are functional.
FIG. 2 shows flow diagrams for the prior art test arrangement shown in FIG. 1. The test unit transmits the test data via a data line at a high clock frequency and subsequently reads them from the data store again On each data line in the data bus, the test unit receives a test data sequence, which comprises four test data in the example shown in FIG. 2. Such a test data sequence is also referred to as a data burst. The test unit produces an internal strobe signal, with each strobe signal involving a received test data item being compared with a stored reference data item within the test unit, so that data discrepancies can be ascertained. These data discrepancies indicate that the addressed memory cell within the data store is faulty. Modern data stores work at ever higher operating clock frequencies, which means that the data transmission rates at which the test data are written to the memory cells and are subsequently read again are likewise becoming higher and higher. For this reason, the operating clock frequency of the external test unit, in which the test data which have been read are evaluated, likewise needs to be increased. In the example shown in FIG. 2, the clock frequency of the strobe signal corresponds to the data transmission rate of the test data which have been read. With the increasing data transmission rate of the semiconductor memory which is to be tested, it is therefore necessary for the test unit to be adapted accordingly in the test arrangement shown in FIG. 1. The ever shorter development cycles for developing modern data stores working at ever higher data transmission rates mean that the test units used heretofore can no longer be used for testing developed data stores in many cases. At very high data transmission rates for the data store which is to be tested, test units which have relatively complex circuitry and are thus cost intensive are therefore required.